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Worked example
Real numbers from this tool, line by line.
Yosys migration check found 6 findings in one Vivado board top, the kind of top.v an FPGA engineer in the US or EU carries out of a Vivado project: a clk_wiz_0 IP instance, an xpm_cdc_single macro, a mark_debug attribute, an xpm_memory_sdpram macro, an ila_0 debug core and a `pragma protect encrypted block.
What AMD changed, and when
Starting with the Vivado 2026.1 release (June 2026), AMD moved the Vivado Design Suite to tiered licensing. According to AMD's licensing page, BASIC is a free, annually renewed subscription with limited simulation and debug support. CORE is $1,200 per node-locked seat per year ($1,800 floating). PRO is $2,400 node-locked. ENTERPRISE stays a $4,395 perpetual licence. From 2026.1 on, only PRO, ENTERPRISE and GOLD include access to Vivado versions older than 2026.1; BASIC and CORE users keep their old licence file to use older versions.
That is the renewal moment when a team asks how much of its RTL could go through open-source Yosys instead.
Why the first Yosys run is a bad inventory
Run yosys -p "read_verilog -sv top.v; synth_xilinx" on a file that grew up inside Vivado and it stops at the first module Yosys has never heard of. Fix that one, run again, and it stops at the next. Two lines never stop it at all: (* mark_debug = "true" *) and (* DONT_TOUCH = "yes" *) are Vivado behaviour, and when the flow changes they simply stop doing anything.
A chatbot will happily list "Vivado features Yosys lacks", but it answers from memory and never sees your file.
The sample file, line by line
The check reads the file as text, blanks out comments (so // replaced xpm_cdc_single does not count) and applies 12 rules. On _fixtures/dirty.v:
| Vivado-only line | Yosys-ready fix |
|---|---|
| clk_wiz_0 u_clk | RTL or primitive instance |
| xpm_cdc_single | own 2-flop synchroniser module |
| (* mark_debug *) | drop or keep as note |
| xpm_memory_sdpram | inferred reg array RAM |
| ila_0 u_ila | wrap in ifdef VIVADO_DEBUG |
| `pragma protect begin_protected | get plain RTL or rewrite |
The XPM macros are SystemVerilog modules that ship inside the Vivado install, so outside Vivado there is no definition to read. clk_wiz_0 and ila_0 are generated from .xci files by Vivado; the RTL in your repo only holds the instance. An IEEE 1735 protect block can only be opened by the tool that holds the key.
The ported file, _fixtures/clean.v, replaces the synchroniser with a two-flop module the team owns, infers the RAM from a reg array and marks the flop with (* keep *). It gives 0 findings.
The 12 rules
XPM_CDC, XPM_MEMORY, XPM_FIFO, ENCRYPTED_IP, VIVADO_IP_INSTANCE, DEBUG_CORE, MARK_DEBUG, DONT_TOUCH, GLBL_REF (references into Vivado's glbl simulation module), SV_CLASS and SV_COVERGROUP (testbench constructs Yosys does not parse) and VIVADO_PROJECT_PATH (paths into project.srcs/, .gen/, .runs/ or .ip_user_files/).
Try it on your own file
Paste a .v or .sv file into the free web page, or open it in VS Code and run the scan from the command palette. The free scan covers the open file with every blocker, its line and its fix. The full version scans every Verilog file in the workspace and exports a Markdown migration report per blocker for the team.
15 seconds — what it actually does
Questions people ask
What does Yosys Migration Check do?
It reads a Verilog or SystemVerilog file and flags every line that only works inside AMD Vivado, using 12 rules. On the sample Vivado board top it gives 6 findings: a clk_wiz_0 IP instance, an xpm_cdc_single macro, a mark_debug attribute, an xpm_memory_sdpram macro, an ila_0 debug core and a pragma protect encrypted block. Each finding comes with a Yosys-ready fix.
Who is Yosys Migration Check for?
FPGA and RTL engineers in the US and EU who are moving some synthesis from AMD Vivado to open-source Yosys, for example after the Vivado 2026.1 tiered licensing change. It suits a team lead sizing the port, a contractor quoting it, or an engineer checking one module before the next Vivado licence renewal.
Why not just run Yosys or ask a chatbot?
A Yosys run stops at the first missing module, such as xpm_cdc_single, and says nothing about the next blockers in the file. It also stays quiet about mark_debug and DONT_TOUCH, which are Vivado behaviour that simply disappears. A chatbot answers from memory and does not see your file. This check lists every Vivado-only line at once.
What is free and what does the full version add?
Free: scan the open .v or .sv file and see every Vivado-only blocker with its line number and a Yosys-ready fix, no key and no account, and the file stays on your machine. The full version, 29 dollars once, scans every Verilog file in the workspace and exports a Markdown migration report per blocker for the team.
What does staying on a Vivado licence cost?
From Vivado 2026.1, AMD lists the CORE tier at $1,200 per node-locked seat per year and $1,800 floating, PRO at $2,400 node-locked, and ENTERPRISE at $4,395 perpetual. BASIC is free with limited simulation and debug support. Knowing which files are Vivado-only tells you how much RTL can move to Yosys before that renewal.
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